In semiconductor memory devices circuits are used for selecting/deselecting addressed memory cells. A example circuit is shown in FIG. 1. The circuit comprises a decoding line that includes a plurality of decoding transistors connected in series and which are controlled by respective selection signals DEC<3>, DEC<2>, DEC<1>. The decoding line also includes at least one transistor controlled by an enable/disable signal PGM, and is connected between a node having a regulated voltage VPD and the series of decoding transistors. When a bit-line is selected, the signals PGM, DEC<3>, DEC<2>, DEC<1> enable the respective transistors. In the memory cells, which are substantially transistors, there are non-null voltages.
An important field of application of the invention is to non-volatile Flash memory devices. For this reason reference will be made to these devices, though other types of semiconductor memory devices are applicable. The programming voltage on the drain of Flash memory cells should be regulated to a precise value. This is very difficult without occupying a large area of silicon.
The voltage on the terminals of any memory cell to be programmed (drain-source voltage) depends on the current flowing in the cell (IP<i>), the number of bits to be programmed at the time, the supply voltage of the memory (VCC), and the operating temperature (T). By observing the typical example of column decoding used in Flash memory devices depicted in FIG. 1, the following is noted: PGM<15:0> are on/off signals that enable the pass-transistor depending on whether a certain bit is to be programmed or not; VPD is the regulated voltage commonly generated by a charge pump circuit; DEC<3:1> are selection signals of the column decoding; and BL<i> are local bit-lines.
In a partitioned memory device, wherein 16 cells at a time are to be programmed, there are 16 pass transistors controlled by the PGM signals. There are also N*16 transistors driven by the selection signal DEC<3>, 16*N*M transistors controlled by the selection signal DEC<2>, and 16*N*M*L transistors controlled by the selection signal DEC<1>, wherein N, M and L are all multiples of 2.
The problems that arise when a decoding circuit such as that of FIG. 1 is used are as follows. It is very difficult to form a regulator for the voltage BL on each cell to be programmed because 16*N*M*L voltage regulators would be required. This results in an unacceptable area occupied silicon.
The current flowing in each cell, designed for a certain nominal value, has a spread that becomes larger as the fabrication process becomes less precise. The current flowing in a cell determines a voltage drop on the selection transistors of the relative bit-line path, and in particular, on the selection transistor controlled by the signal DEC<1>. The selection transistors controlled by DEC<1> are as numerous as the cells of a row. They should be accommodated in the cell pitch, thus they are very small. The voltage drop along the bit-line path ΔV(IP) is approximately given by the drop on the transistors controlled by DEC<1> (low level decoding transistors), as depicted in FIG. 2. The voltage on the nodes of the cell is about VPD−ΔV(IP), thus the programming voltage depends on the current absorbed by the single cell.
The functioning temperature is relevant because when it varies, the resistivity of the low level decoding transistors also varies. The regulated voltage VPD generally depends on the total current absorption by all addressed cells. The voltage drop BL<i> on a cell, which depends on the voltage VPD, indirectly depends upon the number of bits (addressed cells) to be programmed.
If the supply voltage VCC varies, the performance of the charge pump circuit also varies as well as the regulated voltage VPD. As a consequence, the programming voltage BL<i> on each cell varies.
Generally, the following equation holds:BL<i>=VPD[ΣIP<i>,VCC]−ΔVIP[T,IP<i>]Keeping the voltage drop BL<i> on the i-th cell within an acceptable range is difficult when the above parameters vary.
These conditions impose a compromise in which the programming voltage may differ from its nominal value. This compromise may be tolerable in some classes of memory devices. However, it becomes impracticable in multi-level memory devices where the drain voltage on the cells needs to be precisely determined.